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Freescale Semiconductor /MK21D5WS /PIT /MCR

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Interpret as MCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FRZ 0 (0)MDIS 0RESERVED 0RESERVED

MDIS=0, FRZ=0

Description

PIT Module Control Register

Fields

FRZ

Freeze

0 (0): Timers continue to run in Debug mode.

1 (1): Timers are stopped in Debug mode.
MDIS

Module Disable - (PIT section)

0 (0): Clock for standard PIT timers is enabled.

1 (1): Clock for standard PIT timers is disabled.
RESERVED

no description available
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data